Liquid display devices for use in various fields from compact cellular phones to more than 30-inch large-size televisions are classified into simple matrix type liquid crystal display devices and active matrix type liquid crystal display devices according to the driving method of pixels. Out of these, an active matrix type liquid crystal display device having a thin film transistor (which is hereinafter referred to as a TFT) as a switching element can implement a high precision image quality; and is adaptable to high-speed images or the like, and hence it has been used for general purposes.
With reference to FIG. 1, a description will be given to the configuration and the operational principle of a typical liquid crystal display to be applied to an active matrix type liquid crystal display device. Herein, the description will be given by taking a TFT substrate using hydrogenated amorphous silicon as an active semiconductor layer (which may be hereinafter referred as an amorphous silicon TFT substrate) as a typical example, which is non-limiting. A TFT substrate using polysilicon is also acceptable.
As shown in FIG. 1, the liquid crystal display has a TFT substrate 1, an opposing substrate 2 disposed opposite the TFT substrate 1, and a liquid crystal layer 3 disposed between the TFT substrate 1 and the opposing substrate 2, and functioning as an optical modulation layer. The TFT substrate 1 has a TFT 4 disposed on an insulating glass substrate 1a, a transparent pixel electrode 5, and a wiring part 6 including a scanning line and a signal line. The transparent pixel electrode 5 is formed of a conductive oxide film such as an indium tin oxide (ITO) film comprising tin oxide (SnO) in an amount of about 10 mass % in indium oxide (In2O3). The TFT substrate 1 is driven by a driver circuit 13 and a control circuit 14 connected through a TAB tape 12.
The opposing substrate 2 has, on the TFT substrate 1 side, a common electrode 7 formed over the entire surface of an insulating glass substrate 1b, a color filter 8 disposed at position opposite the transparent pixel electrode 5, and a light shield film 9 disposed in a position opposite the TFT 4 and the wiring part 6 on the TFT substrate 1. The opposing substrate 2 further has an alignment film 11 for aligning liquid crystal molecules (not shown) comprised in the liquid crystal layer 3 in a predetermined orientation.
On the outsides of the TFT substrate 1 and the opposing substrate 2 (on the opposite sides from the liquid crystal layer 3 side), polarizing plates 10 are disposed, respectively.
With the liquid crystal display, the alignment direction of liquid crystal molecules in the liquid crystal layer 3 is controlled by the electric field formed between the opposing electrode (not shown) and the transparent pixel electrode 5. Thus, the light passing through the liquid crystal layer 3 is modulated. As a result of this, the amount of light passing through the opposing substrate 2 is controlled, so that an image is displayed.
Then, with reference to FIG. 2, the configuration and the operational principle of a conventional amorphous silicon TFT substrate to be preferably used for a liquid crystal display will be described in details. FIG. 2 is an enlarged view of the essential part of A in FIG. 1.
As shown in FIG. 2, on a glass substrate (not shown), a scanning line (gate wire) 25 is formed. A part of the scanning line 25 functions as a gate electrode 26 for controlling ON/OFF of the TFT. A gate insulation film (silicon nitride film) 27 is formed in such a manner as to cover the gate electrode 26. A signal line (source-drain wire) 34 is formed in such a manner as to cross with the scanning line 25 via the gate insulation film 27. Thus, a part of the signal line 34 functions as a source electrode 28 of the TFT. On the gate insulation film 27, an amorphous silicon channel film (active semiconductor film, not shown), the signal line (source-drain wire) 34, and an interlayer insulation silicon nitride film (protective film) 30 are sequentially formed. This type is generally also referred to as a bottom gate type.
The amorphous silicon channel film includes an intrinsic layer not doped with P (phosphorus) (i layer, which is also referred to as a nondoping layer), and a doped layer (n layer) doped with P. In the pixel region on the gate insulation film 27, for example, the transparent pixel electrode 5 formed of an ITO film comprising SnO in In2O3 is disposed. The drain electrode 29 of the TFT is electrically connected to the transparent pixel electrode 5.
When a gate voltage is supplied to the gate electrode 26 via the scanning line 25, the TFT 4 is rendered in an ON state. Thus, the driving voltage previously supplied to the signal line 34 is supplied from the source electrode 28 to the transparent-pixel electrode 5 via the drain electrode 29. Then, when a driving voltage at a predetermined level is supplied to the transparent pixel electrode 5, as described in connection with FIG. 1, a potential difference is caused between the transparent pixel electrode 5 and the opposing electrode. As a result, the liquid crystal molecules comprised in the liquid crystal layer 3 are aligned, so that optical modulation is carried out.
In the TFT substrate 1, the signal line (signal line for the pixel electrode) to be electrically connected to the transparent pixel electrode 5, the source-drain wire 34 to be electrically connected to the source electrode 28-drain electrode 29, and the scanning line 25 to be electrically connected to the gate electrode 26 are all formed of a thin film of pure Al or an Al alloy such as Al—Nd (which is hereinafter referred to as an Al type thin film in the column of Background art) because of the low electric resistivity, ease of micromachining, and other reasons. Thereon and thereunder, as shown in FIG. 2, there are formed barrier metal layers 51, 52, 53, and 54 including a refractory metal such as Mo, Cr, Ti, or W.
Herein, the reason why the Al type thin film is connected to the transparent pixel electrode 5 via the barrier metal layer 54 is as follows. When the Al type thin film is directly connected to the transparent pixel electrode 5, the coupling resistance (contact resistance) increases, resulting in degradation of the display quality of the screen. Namely, Al forming the wire to be directly connected to the transparent pixel electrode is very susceptible to oxidation. Thus, by oxygen formed in the process of deposition of the liquid crystal display, oxygen to be added during deposition, or the like, an insulation layer of an Al oxide is formed at the interface between the Al type thin film and the transparent pixel electrode. Further, the ITO forming the transparent pixel electrode is a conductive metal oxide. However, electric ohmic coupling cannot be carried out due to the Al oxide layer formed in the foregoing manner.
However, in order to form the barrier metal layer, a deposition chamber for barrier metal formation must be additionally mounted in addition to a sputtering device for deposition necessary for the formation of the gate electrode and the source electrode, and further the drain electrode. With the advance of reduction of cost with the trend for the mass production of liquid crystal displays, the increase in manufacturing cost and the reduction of the productivity entailed by formation of the barrier metal layer have become impossible to disregard.
Under such circumstances, there have been proposed wiring materials and manufacturing methods of electrodes and the like which can omit the formation of the barrier metal layer, and enables direct coupling of the Al type thin film to the transparent pixel electrode.
For example, in Patent Document 1, there is disclosed a technology using an indium zinc oxide (IZO) film comprising zinc oxide in an amount of about 10 mass % in indium oxide as a material for the transparent pixel electrode. However, with this technology, the currently most commonly used ITO film must be changed to an IZO film, resulting in an increase in material cost.
In Patent Document 2, there is disclosed a method in which a drain electrode is subjected to a plasma treatment or ion implantation to modify the surface of the drain electrode. However, with this method, a step for surface treatment is added, resulting in reduction of productivity.
Whereas, in Patent Document 3, there is disclosed a method in which as a gate electrode, a source electrode, and a drain electrode, a first layer of pure Al or Al, and a second layer comprising impurities such as N, O, Si, or C in pure Al or Al are used. With this method, there is an advantage in that the thin films forming the gate electrode, the source electrode, and the drain electrode can be continuously formed by means of the same deposition chamber. However, a step of forming the second layer comprising the impurities is additionally imposed. Further, in the process of introducing impurities to the source-drain wire, a phenomenon that deposits of the source-drain wire flake off as flakes from the wall surface of the chamber frequently occurs due to the difference in coefficient of thermal expansion between the film including impurities mixed therein and the film not including impurities mixed therein. In order to prevent this phenomenon, it is necessary to frequently stop the deposition step, and to carry out maintenance, resulting in remarkable reduction of productivity.
In view of such circumstances, there is disclosed a method enabling omission of the barrier metal layer, and achieving simplification without increasing the number of steps, and thus capable of coupling the Al alloy film to the transparent pixel electrode directly and surely (Patent Document 4). In Patent Document 4, as the alloy component, an Al alloy comprising at least one selected from a group consisting of Au, Ag, Zn, Cu, Ni, Sr, Ge, Sm, and Bi in an amount of 0.1 to 6 at % is used. By allowing at least a part of these alloy components to be present as a deposit or a concentrated layer at the interface between the Al alloy film and the transparent pixel electrode, the foregoing problem is solved.
In Patent Document 4, for example, in the case of Al—Ni type alloys, the electric resistivities after a heat treatment at 250° C. for 30 minutes are as low as 3.8 μΩ·cm for Al-2 at % Ni, 5.8 μΩ·cm for Al-4 at % Ni, and 6.5 μΩ·cm for Al-6 at % Ni. Thus, when an Al alloy film thus controlled low in electric resistivity is used, the power consumption of the display device can be reduced, which is very useful. Further, when the electric resistivity of the electrode part decreases, the time constant determined by the product of the electric resistance and the electric capacitance also decreases. Therefore, even when the display panel is increased in size, it becomes possible to keep the high display quality. However, the heat resistance temperatures of the Al—Ni type alloys are all as low as roughly 150 to 200° C.
Then, in Patent Document 5, there is disclosed a thin film transistor substrate having a thin film transistor and a transparent pixel electrode, wherein Al alloy film and a conductive oxide film are directly connected with each other not via a refractory metal, and in the direct coupling interface, a part of, or the whole of the Al alloy component is present in a precipitated or concentrated form. The Al alloy film is a thin film transistor substrate including an Al-α-X alloy comprising, as alloy components, an element belonging to the group α in an amount in the range of 0.1 at % or more and 6 at % or less, and an element belonging to the group X in an amount in the range of 0.1 at % or more and 2.0 at % or less. The element belonging to the group α is at least one element selected from the group consisting of Ni, Ag, Zn, Cu, and Ge. The element belonging to the group X is at least one element selected from the group consisting of Mg, Cr, Mn, Ru, Rh, Pd, Ir, Pt, La, Ce, Pr, Gd, Tb, Sm, Eu, Ho, Er, Tm, Yb, Lu, and Dy.
It is regarded that use of the thin film transistor substrate enables omission of the barrier metal layer, and enables direct and reliable coupling of the Al alloy film to the pixel electrode including a conductive oxide film without increasing the number of steps. Further, it is regarded that, even when a heat treatment temperature as low as, for example, about 100° C. or more and 300° C. or less is applied to the Al alloy film, reduction of the electric resistivity between the pixel electrodes and excellent heat resistance can be achieved. Specifically, the following is described: for example, when a heat treatment at a temperature as low as 250° C.×30 minutes is adopted, it is possible to attain 7 μΩ·cm or less in terms of the electric resistivity of the Al type alloy thin film without causing defects such as hillocks.
Whereas, in Patent Document 6, there is described an Al alloy film for a wiring film comprising, as additional elements, Ge in an amount of 0.2 to 1.5 at %, and further comprising Ni in an amount of 0.2 to 2.5 at %, and the balance including Al. However, according to Table 1 of Patent Document 6, it is difficult to satisfy both the low electric resistivity and the favorable surface conditions.
On the other hand, in recent years, with a trend for a higher image quality and a higher definition of a liquid crystal display, miniaturization of the wire for an Al alloy film electrode (miniaturization of line width) has been advanced. Accordingly, the method of wiring formation has been being changed from a conventionally generally used wet etching method (a method for carrying out wiring patterning by etching with a chemical liquid) to a dry etching method (a method for carrying out wiring patterning by etching with a reactive plasma). With the wet etching method, there occurs a phenomenon called “side etching” that the chemical liquid runs to the underlying side of a resist which is a mask for patterning to etch the wiring sidewall. Therefore, it is difficult to precisely control the wiring dimensions/shape. In contrast, with a dry etching method, it is possible to carry out precise etching, and hence the method is excellent in fine processing of wiring. With dry etching, fine wiring with a line width of 2 μm or less can be formed. Whereas, when all the etching steps in TFT manufacturing can be carried out through dry etching, improvement of productivity can also be expected.
Thus, as a film for electrodes/a film for wiring suitable for dry etching, in Patent Document 7, there is disclosed an Al—Nd type alloy thin film comprising Nd in an amount of more than 0.1 at % to 1.0 at % in Al. However, the Al alloy thin film cannot be directly connected to transparent pixel electrodes.    Patent Document 1: Japanese patent laid-open No. 11-337976    Patent Document 2: Japanese patent laid-open No. 11-283934    Patent Document 3: Japanese patent laid-open No. 11-284195    Patent Document 4: Japanese patent laid-open No. 2004-214606    Patent Document 5: Japanese patent laid-open No. 2006-261636    Patent Document 6: Japanese patent laid-open No. 2005-171378    Patent Document 7: Japanese patent laid-open No. 2004-55842